Make utility in Unix. Make over different directories

[tomPee]

Hi,

I have no idea if this is the right section to post this in. But i thought it maybe belonged here most.

The problem i having is actually, most likely really simple. But here i am running for help. I have read a lot about make files, but well, not a single one actually sais something about the approach i'm using.

Which ofcourse might perfectly mean i'm doing something completely wrong. :P.

Well, I'll cut the case.

I've divided my source over 4 different directories.
there are the:
-api
-test
-plugins
-main

directories. The main.cpp file is in the main directorie.
In the 'src' directory. Where all these subdirectories are in, is the makefile i'm using.

The main.cpp file needs to be linked with .o files from, well all the different maps. But i hope that isn't a problem.

SOURCES := /main/main.cpp \
    /api/product.cpp \
    /api/basicObject.cpp \
    /api/productList.cpp \
    /api/ingredient.cpp \
    /api/ingredientList.cpp \
    /api/controlUnit.cpp \
    /tests/productTest.cpp \
    /tests/productListTest.cpp \
    /tests/ingredientTest.cpp \
    /tests/ingredientListTest.cpp \
    /api/review.cpp \
    /tests/reviewTest.cpp \ 
    /api/reviewList.cpp \
    /tests/reviewListTest.cpp \
    /api/step.cpp \
    /tests/stepTest.cpp \
    /api/preparation.cpp \
    /tests/preparationTest.cpp \
    /api/recipe.cpp \
    /tests/recipeTest.cpp \
    /api/cookBook.cpp \
    /tests/cookBookTest.cpp \
    /plugins/createCookBook.cpp \
    /plugins/printerUnformatted.cpp
DEP := $(SOURCES:.cpp=.d)
OBJECTS := $(SOURCES:.cpp=.o)
EXE := cookBook
CC := g++ -Wall
 
all: $(EXE)
 
%.d:%.cpp
    $(CC) -MM $< -o $@
 
include $(DEP)
 
$(EXE): $(OBJECTS)
    $(CC) -o $@ $?
 
 
$(OBJECTS):
    $(CC) -c -o $@ $<
 
.PHONY: clean
clean:
    rm -f cookBook *.o *.d
 
.PHONY: doc
doc:
    rm -f *.d
    @doxygen
 
 

That is the makefile i'm using.
The error i'm getting is the following:

tom@tomP:~/UNI-FILES/2ba/Gevorderd_Progr ameren/CookingBook/src$ make
Makefile:14: *** commands commence before first target. Stop.

Now, i have absolutely no idea what i am doing wrong. I'd just like to be able to split my code over different maps and still keep the makefile logic reasonably simple.

Does anyone have any suggestions on how to do this ? I'm really tired of trying to figure this out. I've tried before, i've tried again now. But I just can't think of what i'm doing wrong.
And probably it's something really simple and stupid, I just don't know what.

Any help is really appreciated.
Thanks a million in advance !!!

-Tom