question on Makefile

[srikar]

Hi can any one explain me the reason.

For any Makefile there will be assosiated rules file, may be in same directory or in other directory. What is the need for this rules file.

Is it that commands in the makefile will gets executed depending on the rules.
or
If we have dependencies for the tagets in the Makefile, than the commands used to generate the target will be present in rules file.

we can write the command for dependencies in the make file itself.
than what is the need of rules file.

Please explain me I having lot of confusion with this rules file.


regards

srikar

[Banfa]

Generally the rules files just contains default rules that may be useful, for instance that an obj file is created from a c file by calling the compiler.

There is no absolute need for the rules file it just generally makes things easier by putting all the common stuff into a single file leaving the make file to just declare the actual dependecies for the specific project.

[srikar]

Generally the rules files just contains default rules that may be useful, for instance that an obj file is created from a c file by calling the compiler.

There is no absolute need for the rules file it just generally makes things easier by putting all the common stuff into a single file leaving the make file to just declare the actual dependecies for the specific project.

Thanks Banfa, For the immediate response.
But I am still having some queries in my mind.

In my project I am having a Makefile and in this file , site.rules file is being
included, I am having some dependencies and assosiated commands in the site.rules. Is it that if the target corresponding to this dependecy is not mentioned in the Makefile than will that Target will get generated or not.
please clarify me.
the target I am having in rules file is

$(BIN_DIR)/lex.yy.$(OBJ_EXT) : $(BIN_DIR)/lex.yy.c
ifdef ARCH_nt
@cd $(BIN_DIR); \
$(CC) -c $(CPPFLAGS) -I../../src $(CFLAGS) $(notdir $<) $(CC_OUT_OPTION)$(notdir $@)
else
@$(CC) -c $(CPPFLAGS) $(CFLAGS) $< $(CC_OUT_OPTION)$@
endif
I am working on amd64 machine.
once again Thank you Banfa
regards
srikar

[Banfa]

I would say that this defines a rule that compiles lex.yy.c.

However if in your make file you do not state that your makefiles main target (whatever that is) is dependent on lex.yy.$(OBJ_EXT) then this rule will never come into play.

Make files are heirarchical, there is the main target (which is the target given on the command line or if non target given on the command line either the first or the last target in the file depending on which make engine you are using) and only files which are dependents or sub-dependents of the main target will have their rules executed.

where a sub-dependent is a dependent of either a dependent or another sub-dependant.

[srikar]

Thank you Banfa