Makefile

[newbiecpp]

I am very sorry to post this one because I know it is out of topic but I
cannot find the proper news group. I understand that most senior C++
programmers know makefile very well. My question is GNU makefile support
command line argument?

I want to write a makefile so that when you invoke "make test", the makefile
will compile test like this:

$project = "command line argument, i.e., test";

$project : ($project).cpp
g++ -ggdb -o $project ($project).cpp

I cannot figure it out how I can get $project=test, the test is from command
line argument. I appreciate any help or direct me to the right new groups.

Thanks in advance!

[Alwyn]

In article <yDlYc.3487$hq5 .2435@trndny09> , newbiecpp
<ne*******@yaho o.com> wrote:

I am very sorry to post this one because I know it is out of topic but I
cannot find the proper news group. I understand that most senior C++
programmers know makefile very well. My question is GNU makefile support
command line argument?

I want to write a makefile so that when you invoke "make test", the makefile
will compile test like this:

$project = "command line argument, i.e., test";

$project : ($project).cpp
g++ -ggdb -o $project ($project).cpp

I cannot figure it out how I can get $project=test, the test is from command
line argument. I appreciate any help or direct me to the right new groups.

If your project is so simple, with just one source file to make the
executable. you don't even need a make file for that. You just type
'make test', and it will instruct the compiler to build executable
'test' from 'test.cc'.

For example:

~/Scrap $ ls
newton.caml test.cc
~/Scrap $ cat test.cc
int main()
{
}
~/Scrap $ make test
g++ test.cc -o test
~/Scrap $ ls
newton.caml test test.cc
~/Scrap $ rm test
~/Scrap $ make test CXXFLAGS=-g
g++ -g test.cc -o test
~/Scrap $

HTH

Alwyn

[Rolf Magnus]

newbiecpp wrote:

I am very sorry to post this one because I know it is out of topic but
I cannot find the proper news group.
What about gnu.utils.help?
I understand that most senior C++ programmers know makefile very well.
My question is GNU makefile support command line argument?

I want to write a makefile so that when you invoke "make test", the
makefile will compile test like this:

$project = "command line argument, i.e., test";

$project : ($project).cpp
g++ -ggdb -o $project ($project).cpp

I cannot figure it out how I can get $project=test, the test is from
command line argument.
If you add a command line argument like "test", make will try to find a
target with that name and build it. So to do the above, you'd need to
create a wildcard target that does the right thing. Your above example
is even be built-in to gnu make. Just try the following Makefile:

CXX = g++
CXXFLAGS = -ggdb

On a "make test", it should just do what you asked for above.
I appreciate any help or direct me to the right new groups.

Done. (xpost & f'up to gnu.utils.help)

[Rui Maciel]

newbiecpp wrote:

I am very sorry to post this one because I know it is out of topic but I
cannot find the proper news group. I understand that most senior C++
programmers know makefile very well. My question is GNU makefile support
command line argument?

I want to write a makefile so that when you invoke "make test", the makefile
will compile test like this:

$project = "command line argument, i.e., test";

$project : ($project).cpp
g++ -ggdb -o $project ($project).cpp

I cannot figure it out how I can get $project=test, the test is from command
line argument. I appreciate any help or direct me to the right new groups.

Thanks in advance!

Why not set up a makefile variable for the project name and alter it as
you see fit? It may not be a solution involving command line arguments
but apparently it achieves the same thing.

[Karthik Kumar]

newbiecpp wrote:

I am very sorry to post this one because I know it is out of topic but I
cannot find the proper news group. I understand that most senior C++
programmers know makefile very well. My question is GNU makefile support
command line argument?

I want to write a makefile so that when you invoke "make test", the makefile
will compile test like this:

$project = "command line argument, i.e., test";

$project : ($project).cpp
g++ -ggdb -o $project ($project).cpp

I cannot figure it out how I can get $project=test, the test is from command
line argument. I appreciate any help or direct me to the right new groups.

Thanks in advance!

This has more to do with understanding makefiles than C++ ( Hence
flagging the msg as o.t. ).

make test essentially means a target (test is the target).

Refer to the make utility manual to get this done.
--
Karthik.
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