I'm trying to write a makefile with a conditional statement that uses a variable to specify a C compiler which may be cc or gcc.
I am basically using the example we were given in the notes for this task, but it is giving me error.
This is the code:
Expand|Select|Wrap|Line Numbers
- libs_for_gcc = -lgnu
- normal_libs =
- objects = myApp.o hello.o here.o bye.o
- myApp : $(objects)
- ifeq ($(CC),gcc)
- $(CC) -o myApp $(objects) $(libs_for_gcc)
- else
- $(CC) -o myApp $(objects) $(normal_libs)
- endif
- myApp.o : myApp.c
- cc -c myApp.c
- hello.o : hello.c
- cc -c hello.c
- here.o : here.c
- cc -c here.c
- bye.o : bye.c
- cc -c bye.c
- clean :
- rm -f $(objects)
make: Fatal error in reader: myMakefile, line 6: Unexpected end of line seen
The line 6 is before the 'else' statement.
Can anyone please tell me what is wrong here?? This is very urgent!