I actually wrote a gate level verilog parsing module as part of a
generic netlist manipulating/translating package for work a while
back. It allowed me to do fun stuff like translate verilog to spice
and vice versa, construct netlists from python scripts, and so on.
Although it was one of my earlier python projects, so it was awfully
C-like, not particularly pythonic. I recently wrote up a new version
that was a lot more pythonic, but I haven't added verilog input or
output routines yet, just spice. And my boss might not like me
sending out that code. But in general, verilog gate level stuff isn't
too tricky to parse, buses make things kind of tricky, and there are a
lot of different variations (mine was only really reliable with
Synopsys output). And behavioral level code would be a real nightmare
to parse, I'm sure. It's a shame no one has come up with a nice BNF
to python parser package yet, although I'm pretty sure the BNF for
verilog is pages and pages (well, OK, 12 pages in my verilog book), so
doing a full parser would be a real pain regardless. Anyway, good
luck to you, if you do come up with something good, be sure to keep us
posted! :D
"Boris Boutillier" <bo**************@arteris.net> wrote in message news:<pa****************************@arteris.net>. ..
Hi all,
I'm looking for parsing a Verilog file in my python module,
is there already such a tool in python (a module in progress) to
help instead of doing a duplicate job.
And do you know of some generic parsing module in python, in which you
give some kind of grammar and callbacks ?
Thanks for the help
Boris
