with X Y separate dual-bus
super sub , maybe reverse by freq Y is super-bus
X or Y maybe set to internal base ( default )
X@ X! Y@ Y! ( top of stack X@ y@ --> TOS )
X >X >Y Y>
intelligent mem ( something like CPU16 attached to RAM memory stick )
v.s. intelligent mem manager ( MPS PMP 'plug-n-play' 'lego' chip
where MPS addresses a fixed number of local memories and each local
memory is fixed with it's unique CPU16, what is special about x and y,
in this sense, is the dual-bus mpp architecture , don't vote char anything,
use 16-bit as CELL size, ( minimum ), each CPU16 having X and Y, using
TOS for data transfer and avoid ( internal shared RaqBus type DRAM )
multiplexing of MPS internal shared address bus, A register,
X and Y can be ( segment register two-way-hashed to either bus ( super/sub/
*OR* mapped locally , like additional A registers ) ( DSP dynamics )
looking at a modified 25x, the diagonal of the chip are the CPU16s and
( 20 of the 25x are used for multiplex code ) the 10 buses
are split into two groups of five buses ( each multiplex into single
bus ) in translation of 25x into 256x the other ( non-diagonal processors
) ( 240 of 256 ) maybe protocol hard wired ( for two groups of 16 buses )
however the nice feature of not being wired is the 386 like paging segment
register mapping logics maybe programmed instead of requiring complex
multiplex wire
284 ram 384 stacks
The addition here is that the A register used in 25x, to my understanding,
is a separate memory ( or automatically Ram Bus type DRAM multiplex)
ei in the 256, are 16 memories not requiring X or Y multiplexing,
the important efficiency regiment is efficient de-coupling of the X and Y
registers for using the * MPS * internal memories without A multiplex
( Each CPU16 has own X and Y )
SHA-BOOM
Bernd, how's your time?
If Patriot PTSC wins a patent suit against Intel ( good advertising),
but not Transmeta, the full VLIW is not required ( 4096*16bit is variable)
16-bit is the minimum transfer size, ( or VLIW ( cache control word) burst)
if VLIW is executed from the address bus then a new segment is allocated
and recieves data transfer. ( MPS internal, VLIW cache control word is
encoded with length, xxxx000000000000, is either
allocate a single 16-bit word in MPS cache or an error )
