Systemc?

[eman.abu.samra]

Hi Guys,
I did not find another helpful group to post my question, hope you will
be able to help.
We are using systemC to write simulators for verification purposes.

In one of the simulators we use sc_stop to stop simulation (since an
error has occured), but for some reason this method does not work as it
should. It's supposed to stop the simulation properly (close all files
and exit normally ... etc), but I can see that the simulator keeps
running further. It finishes a little later, but it does not exit (the
simulation is stuck, it does not go back to the prompt).

Has anyone have any experiance with sc_stop? should it be used only
within processes? If this is the case, is there another "healthy" way
to stop simulation?

By the way, the simulation gets stuck only on Windows, on Linux it does
not but it's still the same behavior (continues further the sc_stop
command).

I could not find more documentation on the sc_stop in the systemc
site... so I will be truly gratefull for any help

Thanks a lot in advance
Faith

[Jonathan Mcdougall]

em************@gmail.com wrote:

Hi Guys,
I did not find another helpful group to post my question, hope you will
be able to help.
We are using systemC to write simulators for verification purposes.

Unfortunately, this newsgroup only deals with the C++ language itself,
not with the countless libraries it can be used with.

http://www.parashift.com/c++-faq-lit...t.html#faq-5.9
Jonathan

[Roberto Waltman]

"Jonathan Mcdougall" <jo***************@gmail.com> wrote:

em************@gmail.com wrote:

Hi Guys,
I did not find another helpful group to post my question, hope you will
be able to help.
We are using systemC to write simulators for verification purposes.

Unfortunately, this newsgroup only deals with the C++ language itself,
not with the countless libraries it can be used with.

http://www.parashift.com/c++-faq-lit...t.html#faq-5.9

Jonathan

See:
http://www.systemc.org/web/sitedocs/...ion_forum.html
comp.lang.vhdl
comp.lang.verilog
comp.arch.fpga