Makefiles with multiple targets

[A. Gupta]

I'm compiling a project that I want to have multiple targets
(basically debug and optimized). I would like to just be able to type
'make debug' or 'make optimized' and have the makefile compile the
fields into separate directories.

i.e. if I do make debug, all .o files and the executable should go
into the debug directory (compiled with -g on).
Similarly for the optimized version.

I'm a novice at makefiles, I basically hack at them until they do what
I want them to. Could someone post a sample makefile that could do
this?
This is a simple project with all files in one directory - about 25 c
source files.

Thanks.

[Mike Wahler]

"A. Gupta" <ak*****@eudoramail.com> wrote in message
news:8e**************************@posting.google.c om...

I'm compiling a project that I want to have multiple targets
(basically debug and optimized). I would like to just be able to type
'make debug' or 'make optimized' and have the makefile compile the
fields into separate directories.

i.e. if I do make debug, all .o files and the executable should go
into the debug directory (compiled with -g on).
Similarly for the optimized version.

I'm a novice at makefiles, I basically hack at them until they do what
I want them to. Could someone post a sample makefile that could do
this?
This is a simple project with all files in one directory - about 25 c
source files.

'make' utilites aren't topical here, but:

<OT>
Just create separate makefiles named e.g. 'release' and 'debug'
which specify the desired operations, 'sources', and 'targets',
for each and give the appropriate file name as 'make's argument.
(Assuming of course that your 'make' can use such a filename
argument (all that I've used can).

Also, many 'make' utilites let you use a '#define'-like
feature that lets it do conditional execution, which would
enable you to put everything in one 'make' file. All 'make's
are not equal, so consult the documentation for yours.
</OT>
-Mike

[Xenos]

"Mike Wahler" <mk******@mkwahler.net> wrote in message
news:Tp******************@newsread1.news.pas.earth link.net...

"A. Gupta" <ak*****@eudoramail.com> wrote in message
news:8e**************************@posting.google.c om...

I'm compiling a project that I want to have multiple targets
(basically debug and optimized). I would like to just be able to type
'make debug' or 'make optimized' and have the makefile compile the
fields into separate directories.

i.e. if I do make debug, all .o files and the executable should go
into the debug directory (compiled with -g on).
Similarly for the optimized version.

I'm a novice at makefiles, I basically hack at them until they do what
I want them to. Could someone post a sample makefile that could do
this?
This is a simple project with all files in one directory - about 25 c
source files.

'make' utilites aren't topical here, but:

<OT>
Just create separate makefiles named e.g. 'release' and 'debug'
which specify the desired operations, 'sources', and 'targets',
for each and give the appropriate file name as 'make's argument.
(Assuming of course that your 'make' can use such a filename
argument (all that I've used can).

Also, many 'make' utilites let you use a '#define'-like
feature that lets it do conditional execution, which would
enable you to put everything in one 'make' file. All 'make's
are not equal, so consult the documentation for yours.
</OT>
-Mike

I usually just have the makefile call itself recusively with the desired
directory path, such as:

debug:
$(MAKE) DIR_PATH=blah\blah\blah EXTRA_FLAGS="-g -O0"

optimized:
$(MAKE) DIR_PATH=blah\blah\blah EXTRA_FLAGS="-O2"